The present invention relates to a semiconductor device and a method for controlling a flip-flop, and more particularly, to a semiconductor device including a flip-flop having a retention function, and a method for controlling a flip-flop.
As a technique for reducing power consumption in semiconductor devices, there is a technique of interrupting power supply to arithmetic and logic unit cells that are not operating. This technique can be implemented so that an operation similar to that before the power supply is interrupted can be performed when the power supply is resumed, by using a flip-flop having a retention function for storing data also when the power supply is interrupted.
FIG. 15 is a circuit diagram illustrating a semiconductor device according to a related art. The semiconductor device shown in FIG. 15 includes clock gating circuits 101 and 102 and master-slave flip-flops RFF101 and RFF102 having a retention function. The clock gating circuit 101 includes a flip-flop FF101 and an AND circuit AND101. The flip-flop FF101 is driven by a negative edge of a clock signal CLKIN, and outputs an enable signal EN1 at the timing of the negative edge. The AND101 receives an output (FF101_OUT) of the flip-flop FF101 and the clock signal CLKIN, and outputs a result of a logical AND operation between the output of the flip-flop FF101 and the clock signal CLKIN.
The flip-flop RFF101 is a master-slave flip-flop capable of retaining data when an output (RFF101_CLK_IN) of the AND101 is at a low level. FIG. 16A is a diagram illustrating the flip-flop RFF101 (see Japanese Unexamined Patent Application Publication No. 2008-219491). As shown in FIG. 16A, the flip-flop RFF101 includes an AND circuit AND102. The AND102 receives the output (RFF101_CLK_IN) of the AND101 at one end and a data retention signal (RET signal) at the other end, and outputs a result of a logical AND operation between the output of the AND101 and the RET signal. An output (RFF101_CLK) of the AND102 serves as a clock signal for driving the flip-flop RFF101.
The clock gating circuit 102 includes a flip-flop FF102 and an OR circuit OR101. The flip-flop FF102 is driven by a positive edge of the clock signal CLKIN, and outputs a signal (FF102_OUT) obtained by inverting an enable signal EN2 at the timing of the positive edge. The OR101 receives the output of the flip-flop FF102 and the clock signal CLKIN, and outputs a result of a logical OR operation between the output of the flip-flop FF102 and the clock signal CLKIN.
The flip-flop RFF102 is a master-slave flip-flop capable of retaining data when an output (RFF102_CLK_IN) of the OR101 is at a high level. FIG. 16B is a diagram illustrating the flip-flop RFF102 (see Japanese Unexamined Patent Application Publication No. 2008-219491). As shown in FIG. 16B, the flip-flop RFF102 includes an OR circuit OR102. The OR102 receives the output (RFF102_CLK_IN) of the OR101 at one input and an inverted signal of the data retention signal (RET signal) at the other input, and outputs a result of a logical AND operation between the output of the OR101 and the inverted signal of the data retention signal. An output (RFF102_CLK) of the OR102 serves as a clock signal for driving the flip-flop RFF102.
FIGS. 17 and 18 are timing diagrams each illustrating the operation of the semiconductor device shown in FIG. 15. The flip-flops shown in FIGS. 16A and 17B are respectively used as the flip-flops RFF101 and RFF102. The timing diagram of FIG. 17 shows the operation of the clock gating circuit 101 and the flip-flop RFF101. As shown in FIG. 17, in the semiconductor device shown in FIG. 15, the clock signal CLKIN is fixed at the low level during a period between a timing T102 and a timing T105. During a period between a timing T103 and a timing T104, the RET signal becomes low level and the output (RFF101_CLK) of the AND102 is fixed at the low level.
First, the operation in the case where the enable signal EN1 is at a low level “0” during the period between the timing T102 and the timing T105 will be described. Until the timing T102, the output (RFF101_CLK_IN) of the AND101 and the output (RFF101_CLK) of the AND102 are in synchronization with the clock signal CLKIN. Meanwhile, after a timing T101, the enable signal EN1 becomes low level. As a result, the flip-flop FF101 outputs the signal (FF101_OUT) of low level to the AND101 at the timing T102, or at a negative edge of the clock signal CLKIN. Accordingly, the output (RFF101_CLK_IN) of the AND101 is fixed at the low level. In association with this, the output (RFF101_CLK) of the AND102 is also fixed at the low level. During the period between the timing T103 and the timing T104, the RET signal becomes low level and the output (RFF101_CLK_IN) of the AND101 is fixed at the low level. Accordingly, the output (RFF101_CLK) of the AND102 does not change.
At the timing T105, the clock signal CLKIN resumes operation and the enable signal EN1 becomes high level. As a result, the flip-flop FF101 outputs the signal (FF101_OUT) of high level to the AND101 at a timing T106, or at a negative edge of the clock signal CLKIN. Accordingly, the output (RFF101_CLK_IN) of the AND101 is synchronized with the clock signal CLKIN. Further, since the RET signal is at the high level, the output (RFF101_CLK) of the AND102 is also synchronized with the clock signal CLKIN.
Next, the operation in the case where the enable signal EN1 is at a high level “1” will be described. In this case, the enable signal EN1 is always at the high level, so the flip-flop FF101 always outputs a high-level signal to the AND101. Accordingly, the output (RFF101_CLK_IN) of the AND101 is output in synchronization with the clock signal CLKIN. Since the RET signal is at the high level during periods other than the period between the timing T103 and the timing T104, the output (RFF101_CLK) of the AND102 is also synchronized with the clock signal CLKIN. The RET signal is at the low level during the period between the timing T103 and the timing T104. However, since the clock signal CLKIN is fixed at the low level during the period between the timing T102 and the timing T105, the output (RFF101_CLK) of the AND102 does not change.
Referring next to FIG. 18, the operation of the clock gating circuit 102 and the flip-flop RFF102 will be described. As shown in FIG. 18, in the semiconductor device shown in FIG. 15, the clock signal CLKIN is fixed at the low level during a period between a timing T112 and a timing T115. During a period between a timing T113 and a timing T114, the RET signal is at the low level and the output (RFF102_CLK) of the 0R102 of the RFF102 is fixed at the high level.
First, the operation in the case where the enable signal EN2 is at the low level “0” during the period (between the timing T112 and the timing T115) when the clock signal CLKIN is fixed. Until a timing T111, the output (RFF102_CLK_IN) of the OR101 and the output (RFF102_CLK) of the OR102 are in synchronization with the clock signal CLKIN.
Meanwhile, after the timing T111, the enable signal EN2 becomes low level. As a result, the flip-flop FF102 outputs the signal (FF102_OUT) of high level to the OR101 at the timing T112, or at a positive edge of the clock signal CLKIN. Accordingly, the output (RFF102_CLK_IN) of the OR101 is fixed at the high level. In association with this, the output (RFF102_CLK) of the OR102 of the flip-flop RFF102 is also fixed at the high level. During the period between the timing T113 and the timing T114, the RET signal becomes low level. However, since the output (RFF102_CLK_IN) of the OR101 is fixed at the high level, the output (RFF102_CLK) of the OR102 of the flip-flop RFF102 does not change.
After the timing T115, the clock signal CLKIN resumes operation and the enable signal EN2 becomes high level. As a result, the flip-flop FF102 outputs the signal (FF102_OUT) of low level to the OR101 at a timing T116, or at a positive edge of the clock signal CLKIN. Accordingly, after the timing T116, the output (RFF102_CLK_IN) of the OR101 is synchronized with the clock signal CLKIN. Further, since the RET signal is at the high level, the output (RFF102_CLK) of the OR102 of the flip-flop RFF102 is also synchronized with the clock signal CLKIN.
Next, the operation in the case where the enable signal EN2 is at the high level “1” will be described. In this case, the enable signal EN2 is always at the high level, so the flip-flop FF102 always outputs a low-level signal to the OR101. Accordingly, the output (RFF102_CLK_IN) of the OR101 is output in synchronization with the clock signal CLKIN. Since the RET signal is at the high level during periods other than the period between the timing T113 and the timing T114, the output (RFF102_CLK) of the OR102 of the RFF102 is also synchronized with the clock signal CLKIN.
Meanwhile, the RET signal becomes low level during the period between the timing T113 and the timing T114. At this time, the clock signal CLKIN is fixed at the low level, so the output (RFF102_CLK_IN) of the OR101 is also fixed at the low level. For this reason, when the RET signal input to the OR102 of the REF102 becomes low level at the timing T113, the output (RFF102_CLK) of the 0R102 becomes high level. Further, when the RET signal becomes high level again at the timing T114, the output (REF102_CLK) of the 0R102 becomes low level.
Moreover, Japanese Unexamined Patent Application Publication No. 08-191234 discloses a technique relating to a D flip-flop circuit capable of always generating original output data without limiting the state of a control signal (RET signal) before power saving and the state of the control signal (RET signal) after power saving. The D flip-flop circuit disclosed in Japanese Unexamined Patent Application Publication No. 08-191234 includes a memory circuit which has a positive terminal and a negative terminal and to which another power supply that is different from a power supply used for master and slave units supplies power. The D flip-flop circuit disconnects a path between the negative terminal of the memory circuit and the input terminal of the master unit and a path between the positive terminal of the memory circuit and the input terminal of the slave unit when the D flip-flop circuit is in a power-saving state. In addition, the D flip-flop circuit disconnects the path between the negative terminal of the memory circuit and the input terminal of the master unit when the master unit and the slave unit are disconnected. In short, the use of the D flip-flop circuit disclosed in Japanese Unexamined Patent Application Publication No. 08-191234 enables retention of data at both the low level and the high level of the RET signal.